A conventional planar complementary metal oxide semiconductor (CMOS) transistor has four parts: a source, a drain, a channel disposed between the source and drain, and a gate disposed over the channel to control the channel. In planar CMOS transistors, the source, drain, and channel are formed by implanting ions into a planar semiconductor substrate, and the gate is then formed over a surface of the semiconductor substrate so as to overlie the channel. Engineers continuously seek to shrink the size of such transistors over successive generations of technology to “pack” more transistors into a given unit area, which provides consumers with devices that exhibit improved functionality.
One of the more recent advances in this continuing effort to shrink the size of CMOS transistors is the advent of fin field effect transistors (FinFETs). Unlike planar CMOS transistors where the source, drain, and channel are formed in a planar substrate; in FinFETs the source, drain, and channel region are formed in a thin slice of semiconductor material (i.e., a “fin”), which extends upward from the semiconductor substrate. A chip in advanced CMOS consists of various blocks, including robust electrostatic discharge (ESD) protection. This patent application presents improved silicon controlled rectifier (SCR) devices for bulk FinFET technology.